This invention relates generally to metallization systems and methods and more particularly to metallization systems and methods suitable for use with very large scale integrated (VLSI) circuits. More particularly, the invention relates to metallization systems having increased electromigration (EM) resistance.
As is known in the art, electromigration (EM) in on-chip electrical interconnects is one of the wearout mechanisms which limit the lifetime of integrated circuits. On-chip interconnects are typically made of highly-conductive, polycrystalline metal films, such as aluminum, copper, or their alloys. In such films, electromigration typically proceeds along the network of grain boundaries. EM failures, in the form of voids or hillocks, usually occur at certain grain-boundary intersections, called xe2x80x9ctriple pointsxe2x80x9d, where flux divergence exists, i.e., the flux of metallic atoms entering the intersection is different from the flux of atoms leaving this intersection. However, EM failure is even more likely to occur at the end of a metal conductor where it is attached to an interlevel contact or via. At the same time, as discussed in a paper entitled, xe2x80x9cElectromigration in thin aluminum films on titanium nitridexe2x80x9d by I. A. Blech, published in the Journal of Applied Physics, Vol. 47, No. 4, April 1976, pages 1203-1208, EM voids and hillocks cannot develop in metal lines or conductors which are shorter than a certain xe2x80x9ccritical lengthxe2x80x9d. The xe2x80x9ccritical lengthxe2x80x9d effect was observed in Al/W/Al via chains as reported in xe2x80x9cEvidence of the electromigration short-length effect in aluminum-based metallurgy with tungsten diffusion barriersxe2x80x9d by Ronald G. Filippi et al, Proceedings of MRS Symposium, Vol. 309, 1993 pages 141-148 and in a paper entitled xe2x80x9cPermitted Electromigration of Tungsten-Plug vias in Chain for Test Structure with Short Inter-Plug Distancexe2x80x9d, by T. Aoki et al., published in Proceedings of VMIC Conference, 1994 beginning at page 266. The critical length effect in all-aluminum lines with polycrystalline segments has been reported in a paper entitled xe2x80x9cTwo Electromigration Failure Modes in Polycrystalline Aluminum Interconnectsxe2x80x9d, by E. Atakov, J. J. Clement and B. Miner, published in the Proceeding of the IRPS, 1994, beginning at page 213. At typical operating conditions of silicon integrated circuits, the critical length is expected to be at least 100 um, as discussed in the above reference papers.
Prolongation of the lifetime of a contact to the silicon substrate by forming a gap in one layer of a multilayered metal line within the critical distance from the contact, and filling the gap with a refractory metal has been reported in a paper entitled xe2x80x9cAn Increase of the Electromigration Reliability of Ohmic Contacts by Enhancing Backflow Effectsxe2x80x9d, by Wei Zhang, et al., Proceedings of the IRPS, 1995, beginning at page 365. As described in the Zhang et al. paper, a 4000 xc3x85 thick Al-1% Si electrically conductive film is deposited over a 4700 xc3x85 thick dielectric layer and through a contact opening formed in a region of a dielectric layer to make electrical contact with an electric device formed in a semiconductor body, as shown in FIG. 1 of the paper. The Al-1% Si layer is patterned to form a stripe which is attached to the contact and has a gap at a critical distance, Lc, from the contact. A 3200 xc3x85 thick trilevel metallization layer made of 100 xc3x85 thick Ti, 3000 xc3x85 thick W, 100 xc3x85 thick Ti is deposited over the substrate, covering the Al-1% Si stripe and filling the gap. Next a 4000 xc3x85 thick Al-1% Si layer is deposited over the surface. Because the gap presumably has a depth of the thickness of the first Al-1% Si layer (i.e., a depth of 4000 xc3x85), it appears that the resulting metal surface is non-planar.
The two top metallization layers are patterned to form a stacked stripe coincident with the first Al-1% Si stripe. The first stripe itself is non-planar, making it difficult to perform photolithography to align the stacked stripe. Because of non-planarity, the process described by Wei Zhang, et al. does not ensure the dimension control which is required to fabricate devices with submicron feature size. Particularly, it cannot easily be used to fabricate the conductors in high-performance, state-of-the-art Very Large Integrated Circuits (VLSI).
One of the requirements for metal interconnects in such circuits is that the equidistant conductors be spaced at submicron distance. Very tight dimensional control is required for the fabrication process to ensure such small distance without causing unintended electrical shorts between the conductors.
Also, the structure proposed by Wei Zhang et al., does not provide complete blocking of electromigration, because aluminum can migrate away from the contact in the top conducting layer of Al-1% Si. On the other hand, even though the gap can somewhat prolong the life of the nearby contact, the gap itself creates a flux divergence and is a likely site for an EM failure.
Interconnect structures with a plurality of high electrically conductive, electromigration-prone segments separated by very short, electromigration-resistant refractory metal segments were proposed in U.S. Pat. No. 5,439,731, entitled Interconnect Structures Containing Blocking Segments to Minimize Stress Migration and Electromigration Damage, by Li et al., issued on Aug. 8, 1995.
However, Li et al., propose that the high electrically conductive segments be formed first, and the gaps between the segments be filled with EM-resistant metal afterwards. Another photolithography/metal etch step is required to form the intended interconnect structure. This method has the same disadvantage as the method proposed by Wei Zhang, et al.
Conductors in high-performance VLSI are required to have as low electrical resistance as possible. The EM-resistant refractory metals are known to have a lower electrical conductivity than Al, Au, Cu, etc. For this reason, it is critical that the method which is used to form the interconnect structures allow for making the EM-resistant segments as short as possible.
Also for the purpose of reducing the overall resistance of segmented conductors, it is desirable that the high electrically conductive segments be as long as possible, without compromising the conductor reliability. Li et al., propose that the high electrically conductive segments be as short as 5 to 20 microns. However, it was shown that the high electrically conductive segments are immune to electromigration if they are no longer than the critical length, Lc. As discussed by I. A. Blech, Lc is inversely proportional to the electrical current density in the conductor, and Lc depends on the physical characteristics of the conductor and the overlying dielectric. Lc can be determined using special experimental techniques. As shown by R. G. Filippi et al., and T. Aoki et al., Lc can be as long as 100 um or even longer for state-of-the-art VLSI conductors at typical VLSI operating currents.
In accordance with the invention, a method is provided for forming at least one electrical conductor having a plurality of relatively high electrically conductive segments separated by, and electrically interconnected through, relatively short electromigration-inhibiting/electrically conductive segments, or plugs. The electromigration-inhibiting/electrically conductive segments are formed within a planar surface. More particularly, windows are formed in the planar surface. The windows are filled with electromigration-inhibiting/electrically conductive material to thereby form the plugs, upper portions of the electromigration-inhibiting/electrically conductive material extending above the planar surface. The upper portions of the electromigration-inhibiting/electrically conductive material extending above the planar surface are removed to form the plugs with surfaces co-planar with the aforementioned planar surface. The plugs are separated from each other by a distance less than, or equal to, a predetermined critical length, Lc. Typically, Lc is at least 100 microns, and the electromigration-inhibiting/electrically conductive plugs are shorter, in length, than one micron.
The relatively high electrically conductive segments are formed within the same planar surface as the plugs, either before, or after the plug formation, in such a way that these segments are co-planar with, and abutting, the plugs.
With such method, such formed electrical conductors have improved electromigration resistance, low electrical resistance, and can be readily formed at submicron distance to each other, as required for metallization in high-performance VLSI.
According to one feature of the invention, an electrical conductor is produced by forming a plurality of windows within a planar surface. The windows are aligned along the desired path of the electrical conductor with a space, or distance, between adjacent windows of less than, or equal to, the critical length, Lc. The number of windows is equal to or more than (L/Lc)xe2x88x921 where L is the desired length of the conductor. The dimension, Wp, of each window along the path of the electrical conductor is the minimum width allowed by the given technology, and preferably should be less than, or equal to, one micron. This dimension is further referred to as the window width. The window dimension orthogonal to the path of the electrical conductor, Lp, is at least as large as the desired width, Wc, of the electrical conductor. This dimension is further referred to as the window length. The window depth, Dp, is approximately the same as the desired thickness, Dc, of the electrical conductor, and preferably less than, or equal to, one micron.
An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows. Because of the small width of the windows, the material fills them up completely, with upper portions of such material extending above the planar surface and the windows, and the upper portions of the material deposited above the windows are nearly co-planar with the material deposited above the surrounding planar surface. The upper portion of the material above the windows and the surrounding planar surface is then removed, to form plugs in the windows with surfaces co-planar with the surrounding surface. The relatively high electrically conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation with surfaces co-planar with the plugs, aligned with and abutting the plugs, and electrically interconnected through the plugs.
Such process sequence ensures a very short length, and, consequentially, low resistance of electromigration-inhibiting segments. With the conductive segments being relatively long, the overall resistance increase caused by the electromigration-inhibiting segmentation is very small. The improved electromigration-inhibiting resistance of the resulting electrical conductors is ensured by keeping the length of the electrically conductive segments equal to or less than the predetermined critical length, Lc.
The method also ensures adequate control of the space between equidistant electrical conductors when this space is required to be less than 1 micron. A plurality of equidistant electrical conductors spaced at less than 1 micron can thereby be accurately formed within one layer of metallization using photolithography and dry etching, and multiple layers of metallization can be fabricated in the same way.
In one embodiment of the invention, the planar surface is formed by a relatively high electrically conductive film. The windows, which are at least as deep as the thickness of the relatively high conductive film, are formed in the surface. The electromigration-inhibiting/electrically conductive material is deposited over the conductive film and into the windows formed therein to provide, in such windows, the plugs, an upper portion of such electromigration-inhibiting/electrically conductive material extending above the planar surface and windows. Subsequently, the upper portion of the deposited material is removed to form the plugs with surfaces co-planar with a surface surrounding the plugs. The relatively high electrically conductive film is patterned to form relatively high electrically conductive segments electrically interconnected through the plugs.
In another embodiment of the invention, the planar surface is formed by a dielectric layer. The electromigration-inhibiting/electrically conductive material is deposited over the dielectric layer and into the windows formed therein to provide the plugs, an upper portion of the material extends above the dielectric layer. The upper portion of the deposited electromigration-inhibiting/electrically conductive material extending above the planar surface is removed to form the plugs with surfaces co-planar with the surface of the dielectric layer surrounding the plugs. Trenches are formed in the surface portions of the dielectric film between and aligned with, the plugs. A relatively high electrically conductive material is deposited over the dielectric layer and into the trenches. Subsequently, portions of the deposited electrically conductive material are removed from the dielectric layer to form, in each one of the trenches, corresponding relatively high electrically conductive segments with surfaces thereof co-planar with each other, with the surface of the plugs, and with the surface of the dielectric layer.
In accordance with another embodiment of the invention, the planar surface comprises a dielectric layer having electrical conductors disposed therein. Windows are formed in the electrical conductors thereby separating the electrical conductors into plurality of relatively high electrically conductive segments. The windows are at least as deep as the thickness of the electrical conductors. The electromigration-inhibiting/electrically conductive material is deposited over the dielectric layer, over the electrical conductors and into the windows to provide, in such windows, the plugs, an upper portion of the material extending above the electrical conductor segments and the dielectric layer. The upper portion of the deposited electromigration-inhibiting/electrically conductive material above the electrical conductive segments and dielectric layer is removed to form the plugs with surfaces co-planar with the surface of the dielectric layer and with surfaces of the relatively high electrically conductive segments.
In accordance with still another feature of the invention, windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive liner and relatively high electrically conductive material are successively deposited into the windows and over the surrounding planar surface, an upper portion of such material extending above the windows and the planar surface. The upper portion of the material extending above the windows and the surrounding planar surface is removed to form plugs in the windows with surfaces co-planar with the surrounding surface. Relatively high electrically conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation, so that the surfaces of said segments are co-planar with the plugs, aligned with and abutting the plugs, and electrically interconnected through the plugs. With such an arrangement, the plugs have even smaller resistance than the plugs consisting only of an electromigration-inhibiting/electrically conductive material.
In accordance with still another feature of the invention, a metallization system is provided comprising a plurality of equidistant electrical conductors separated by a distance smaller than 1 micron. Each of the electrical conductors includes a plurality of electrically conductive segments interconnected by much shorter electromigration-inhibiting segments. The conductive segments are co-planar with the electromigration-inhibiting segments. The electromigration-inhibiting segments within each conductor are spaced at a distance less than, or equal to, Lc.
In accordance with still another feature of the invention, a multilevel metallization system is provided. Electrical devices are formed in a semiconductor substrate. A dielectric layer is disposed over the semiconductor surface. Windows are formed to open contact regions of the devices. The windows are filled with an electrically conductive material to electrically connect the devices with the first metallization level. The first metallization level comprises first electrical conductors each having a plurality of first electromigration-inhibiting/electrically conducting plugs therein. The first plugs have a space, or distance between adjacent plugs, less than, or equal to, Lc. The first plugs have co-planar surfaces. The first electrical conductors comprise pluralities of first electrically conductive segments electrically interconnected through the first plugs. The first electrically conductive segments are co-planar with each other and the first plugs. Electrically conductive vias pass through apertures in a dielectric layer disposed on the first metallization system to electrically interconnect the first metallization level and a second metallization level. The second metallization level includes electrical conductors having each a plurality of second electrically conductive segments electrically interconnected through a plurality of second electromigration-inhibiting/electrically conducting plugs. The second plugs have a space, or distance between adjacent ones thereof, less than, or equal to, Lc. The second electrically conductive segments and the second plugs are co-planar. With such an arrangement, the distance between any region of relatively high electrically conductive segments which is near an interlevel via or near a contact to electrical devices, and the nearest electromigration-inhibiting segment never exceeds Lc. Thus, electromigration is suppressed in the relatively high conductive segments, even if they are connected to interlevel vias or contacts to electrical devices.